Flash memory

ABSTRACT

A MONOS Charge-Trapping flash (CTF), with record thinnest 3.6 nm ENT trapping layer, has a large 3.1V 10-year extrapolated retention window at 125° C. and excellent 10 6  endurance at a fast 100 is and ±16 V program/erase. This is achieved using As + -implanted higher κ trapping layer with deep 5.1 eV work-function of As. In contrast, the un-implanted device only has a small 10-year retention window of 1.9 V at 125° C. A MoN—[SiO 2 —LaAlO 3 ]—[Ge—HfON]—[LaAlO 3 —SiO 2 ]—Si CTF device is also provided with record-thinnest 2.5- nm  Equivalent-Si 3 N 4 -Thickness (ENT) trapping layer, large 4.4 V initial memory window, 3.2 V 10-year extrapolated retention window at 125° C., and 3.6 V endurance window at 10 6  cycles, under very fast 100 μs and low ±16 V program/erase. These were achieved using Ge reaction with HfON trapping layer for better charge-trapping and retention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to flash memories, and, more particularly, to aflash memory having a charge-trapping layer formed by implanting arsenicinto ZrON.

2. Description of Related Art

According to International Technology Roadmap for Semiconductors (ITRS),the degraded endurance and retention are the toughest challenges tofurther down-scaling the Charge-Trapping Flash (CTF), due to the fewerelectrons stored in highly scaled device. On the other hand, scalingdown the Si₃N₄ charge-trapping layer to 3-4 nm is needed in ITRS forcontinuous device scaling, but no proposed solution up to now. However,this worsens the retention and endurance due to the poorer trappingcapability at thinner Si₃N₄, where nearly no charge trapping was foundin 2 nm Si₃N₄. Although the retention is improved by using a thickertunnel oxide, this yields reduced erase speed. Such retention anderase-speed trade-off is a basic limitation of CTF.

Previously we addressed this limitation with a deep trapping energyE_(vac)−E_(C) Al(Ga)N or HfON in a metal-oxide-nitride-oxide-Si (MONOS)device. The better retention of high-κ Al(Ga)N MONOS CTF was also listedin ITRS. One drawback of desired higher κ HfON is the lower trappingefficiency; thus, the double trapping HfON—Si₃N₄ CTF was used. Yet thescaling equivalent-Si₃N₄-thickness (ENT) is still limited to 7 nm.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems of the prior art, it is aprimary objective of the present invention to provide flash memory thathas a charge-trapping layer formed by implanting arsenic into ZrON.

In an embodiment of the present invention, the flash memory includes: asubstrate; a first SiO₂ layer formed on the substrate; a first high-κlayer formed on the first SiO₂ layer; a metal-implanted oxynitride layerformed on the first high-κ layer; a second high-κ layer formed on themetal-implanted oxynitride layer; a second SiO₂ layer formed on thesecond high-κ layer; and a gate layer formed on the second SiO₂ layer.

In another embodiment of the present invention, the flash memoryincludes: a Si substrate; a first SiO₂ layer formed on the Si substrate;a first high-κ layer formed on the first SiO₂ layer; a first HfON layerformed on the first high-κ layer; a first Ge/oxynitride layer formed onthe oxynitride layer; a second high-κ layer formed on the Ge/oxynitridelayer; a second SiO₂ layer formed on the second high-κ layer; and a gatelayer formed on the second SiO₂ layer.

The present invention further provides a method of fabricating a flashmemory, including: providing a substrate; forming a first SiO₂ layer onthe substrate; forming a first high-κ layer on the first SiO₂ layer;forming a metal-implanted oxynitride layer on the first high-κ layer;forming a second high-κ layer on the metal-implanted oxynitride layer;forming a second SiO₂ layer on the second high-κ layer; and forming aTaN layer on the second SiO₂ layer.

In an embodiment, the As-implanted ZrON is formed by implanting ZrONwith As at 60°-tilted angle, 3 KeV and 5×10¹⁵ cm⁻² dose, and followed by950° C. RTA.

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the preferred embodiments, with reference madeto the accompanying drawings, wherein:

FIGS. 1( a) to (c) are schematic band diagrams of a traditional MONOSCTF, a double Si₃N₄—HfON trapping CTF, and a As⁺-implanted ZrON CTF,respectively;

FIG. 2 shows J_(g)−V_(g) curves of ZrON MONOS nonvolatile memory (NVM)devices with and without As⁺-implant;

FIG. 3 shows C-V hysteresis of ZrON MONOS NVM devices with and withoutAs⁺-implant;

FIG. 4 shows program characteristics of control ZrON MONOS NVM devicesfor different voltages and times;

FIG. 5 shows erase characteristics of control ZrON MONOS NVM devices fordifferent voltages and times;

FIG. 6 shows program characteristics of As⁺-implanted ZrON MONOS NVMdevices for different voltages and times;

FIG. 7 shows erase characteristics of As⁺-implanted ZrON MONOS NVMdevices for different voltages and times;

FIG. 8 is a schematic structure of an As⁺-implanted ZrON/LaAlO₃/SiO₂/Siof an embodiment according to the present invention;

FIG. 9 shows XRD of control and As⁺-implanted ZrON/LaAlO₃/SiO₂/Sistructure after 950° C. RTA;

FIG. 10 shows SIMS of the As⁺-implanted ZrON/LaAlO₃/SiO₂/Si structureafter 950° C. RTA;

FIG. 11 shows retention characteristics of control un-implanted ZrONMONOS NVM devices at 25-125° C.;

FIG. 12 shows retention characteristics of As⁺-implanted ZrON MONOS NVMdevices at 25-125° C.;

FIG. 13 shows endurance characteristics of As⁺-implanted ZrON MONOS NVMdevices;

FIGS. 14( a) and (b) are a schematic structure and s schematic energyband diagram of a Ge/HfON CTF memory of an embodiment according to thepresent invention, respectively;

FIGS. 15( a) and (b) show program and erase characteristics of HfON CTFmemory with and without Ge for different voltages and times; and

FIGS. 16( a) and (b) show retention characteristics of a flash memoryand cycling characteristics of HfON CTF memory with and without Ge.

DETAILED DESCRIPTION OF THE INVENTION

The following illustrative embodiments are provided to illustrate thedisclosure of the present invention, these and other advantages andeffects can be apparently understood by those in the art after readingthe disclosure of this specification. The present invention can also beperformed or applied by other different embodiments. The details of thespecification may be on the basis of different points and applications,and numerous modifications and variations can be devised withoutdeparting from the spirit of the present invention.

High performance MONOS CTF with highly scaled 3.6 nm ENT is reached andmeets ITRS scaling target for the first time. At 125° C. and ±16 Vprogram/erase (P/E), the device has fast 100 μs speed and largeextrapolated 10-year retention of 3.1 V. The excellent results werereached using metallic Arsenic (As) implant into higher κ ZrON (κ=35) astrapping layer. In contrast, small 10-year retention window of 1.9 V isfound in control ZrON CTF. The improved memory window is due to thebetter electron trapping capability of As⁺-implanted ZrON. The excellent10⁶ cycles and good 125° C. retention may be ascribed to the deepE_(vac)−E_(C) ZrON and 5.1 eV work-function (Φ_(m)) of metallic As, tominimize the Schottky emission and tunnel leakage. The excellent 10⁶cycles are vitally important to allow further endurance improvement inhighly scaled CTF device with fewer electrons. These results comparewell with other reported data listed in Table 1, with the smallest 3.6nm ENT, fast 100 μs speed, large memory window, good retention at 125°C. and the best 10⁶ endurance.

TABLE 1 ΔV_(th) (V) for ΔV_(th) (V) for P/E conditions 10-year 10-yearfor retention & Initial retention retention ΔV_(th) (V) cycling ΔV_(th)(V) @85° C. @125° C. @Cycles This work 16V 100 μs/−16 V 100 μs 4.9 3.43.1 4.3@10⁶ (As⁺-implanted) This work (control 16V 100 μs/−16 V 100 μs2.9 2.1 1.9 — un-implanted) TANOS 13.5 V 100 μs/−13 V 10 ms   4.4  2.07—   4@10⁵ SiO₂/Si₃N₄/Al₂O₃/TaN Tri-gate  11.5 V 3 ms/−11.5 V 100 ms 1.21.1 — 1.5@10⁴ SiO₂/Si₃N₄/SiO₂ (@25° C.) FinFET 13 V 10 μs/−12 V 1 ms 4.5 2.4 — 3.5@10⁴ SiO₂/Si₃N₄/SiO₂ SiO₂/AlGaN/AlLaO₃ 11 V 100 μs/−11 V100 μs  3.0 1.6 — 2.3@10⁵

The TaN—[SiO₂—LaAlO₃]—ZrON—[LaAlO₃—SiO₂]—Si CTF device has 2.5 nmthermal SiO₂, 2.5 nm LaAlO₃, 18 nm ZrON_(0.2), 8 nm LaAlO₃, 6 nm LPCVDSiO₂, and 200 nm TaN. The LaAlO₃, ZrON_(0.2), and TaN were deposited byphysical vapor deposition (PVD). To improve the trapping capability, theZrON was implanted by As at 60°-tilted angle, 3 KeV and 5×10¹⁵ cm⁻²dose, followed by 950° C. RTA to reduce the ion-implanted damage. Aftergate definition, self-aligned As⁺ implant is applied and RTA is used toactivate the dopants. The LaAlO₃ was from binary Al₂O₃ and La₂O₃, usedfor V_(t) tuning in 32 nm gate-first high-κ p- and n-MOSFETs,respectively. For comparison, control CTF device was also fabricatedwithout the As⁺-implant into ZrON.

A. P/E Characteristics:

FIG. 1 shows the traditional, double trapping Si₃N₄—HfON, andAs⁺-implanted ZrON MONOS CTF devices. The As⁺-implanted ZrON has higherκ than HfON and deep Φ_(m) of As for trapping. FIG. 2 shows the gatecurrent (J_(g)) of CTF. Close J_(g) of As⁺-implanted device with controlis reached. Larger C-V hysteresis of 8.1 V was obtained in As⁺-implantedCTF than control device under ±16 V sweep (FIG. 3). FIGS. 4 and 5 showthe program and erase data in control devices. A small ΔV_(th) memorywindow of 2.9 V was measured at 100 μs at ±16 V P/E that is typical formetal-oxide-nitride trapping MONOS with low trapping efficiency. TheΔV_(th) is significantly larger for As⁺-implanted CTF devices shown inFIGS. 6 and 7, with a large ΔV_(th) window of 4.9 V at ±16 V 100 μs P/E.This indicates the better trapping efficiency in As⁺-implanted ZrON thatmay be due to metallic As atoms and implant-created defects. Since a950° C. RTA is applied to lower the implanted defects, the As atoms mayplay a major role for better trapping. The fast 100 μs P/E speed is dueto the existing ΔE_(C) and ΔE_(V) in LaAlO₃/SiO₂ for easier tunneling,where the larger physical thickness improves the retention with only 3nm EOT in tunnel oxide.

B. Characterization of As⁺-Implanted ZrON:

The As⁺-implanted ZrON has a schematic structure shown in FIG. 8, whichwas analyzed by XRD and SIMS shown in FIGS. 9 and 10. As shown in FIG.8, a flash memory 10 of an embodiment according to the present inventioncomprises a substrate 102, a SiO₂ layer 104 formed on the substrate 102,a LaAlO₃ layer 106 formed on the SiO₂ layer 104, an As-implanted ZrONlayer 108 formed on the LaAlO₃ layer 106, another LaAlO₃ layer 110formed on the As-implanted ZrON layer 108, another SiO₂ layer 112 formedon the another LaAlO₃ layer 110, and a TaN layer 114 formed on theanother SiO₂ layer 112. In an embodiment, the SiO₂ layer 104 is 2.5 nmthick; the LaAlO₃ layer 106 is 2.5 nm thick; the As-implanted ZrON layer108 is 18 nm thick; the another LaAlO₃ layer 110 is 8 nm thick; theanother SiO₂ layer 112 is 6 nm thick; and the TaN layer 114 is 200 nmthick. The ZrON poly-grains are found in X-TEM that gives the higher κvalue and smaller ENT. The XRD shows weak As peaks with the same angleof clustered As-dots in As-rich GaAs, which suggests the forming smallAs metal dots in ZrON although beyond our TEM resolution. Such metallicAs with deep 5.1 eV Φ_(m) inside ZrON traps may also reduce the Schottkyemission and tunnel leakage, in addition to the large E_(vac)−E_(C) ofZrON. From SIMS, the As concentration at 60° 3-keV implant reducesrapidly with thickness and mainly within ZrON that explains the closeJ_(g) with control device in FIG. 2.

C. Retention & Endurance:

FIGS. 11 and 12 show the retention data of As⁺-implanted and controlZrON CTF devices at 25, 85 and 125° C. A large 10-year extrapolatedwindow of 3.1 V is measured at 125° C. in As⁺-implanted devices at 100μs and ±16 V P/E. This is significantly better than the 1.9 V 10-yearwindow in control devices. Such large 10-year retention data allowsmulti-level cells (MLC) storage even at 125° C. The good retention isdue to the extra ΔE_(C) confinement energy in LaAlO₃/ZrON/LaAlO₃ andalso deep Φ_(m) of metallic As shown in FIG. 1( c), while fast 100 μserase is also reached from the lowered hole energy barrier ΔE_(V) inLaAlO₃/SiO₂ tunnel oxide. The fast P/E speed and lowered hole tunnelbarrier ΔE_(V) lead to excellent endurance: as shown in FIG. 13, a stilllarge 4.3 V window is obtained even at 10⁶ P/E cycles. Such excellentcycling data are vitally important and allow further improving theendurance in highly scaled CTF device with fewer stored electrons. Table1 compares various MONOS CTF devices. The novel device compares wellwith other devices, with the record thinnest 3.6 nm ENT trapping layer,large memory window, good 125° C. retention, fast 100 μs P/E speed, andthe highest 10⁶ endurance.

Using low energy As⁺-implant into higher κ ZrON trapping layer, thisnovel CTF device shows excellent device performance of highly scaled 3.6nm ENT, large 10-year extrapolated retention window of 3.1 V at 125° C.and 1 million times endurance, at a fast 100 μs and low ±16V P/E.

Among various types of NVM, the flash memory has irreplaceable merits ofthe lowest switching energy and excellent device distribution that arevital for high-density sub-Tb memory arrays. To continue downscale intosub-20-nm, the MONOS CTF devices are proposed to replace the poly-Sifloating-gate (FG) flash memory according to ITRS. This is due to thediscrete charge-trapping property, simple planar structure, and smallcell-cell disturbance that are needed for three-dimensional (3D) flashmemory.

One challenge for CTF is the small confinement energy between Si₃N₄trapping layer and SiO₂ barrier that degrades the high temperatureretention. To address this issue, deep E_(C) high-κ AlGaN and HfON wereused to replace the Si₃N₄, which was listed in ITRS for continuousdownscaling. In addition, we improved the charge-trapping efficiency atan ENT of 3.6-nm, by using As⁺-implanted high-κ trapping layer to reacha large 10-year retention window of 3.1 V at 125° C. However, furtherdownscaling the ENT is limited by the ion-implanted damage to tunneloxide.

In this context, a high performance CTF memory at a record thinnest2.5-nm ENT trapping layer is disclosed for the first time. This devicehas a large extrapolated 10-year retention memory window of 3.2 V at125° C. and excellent endurance of 10⁶ cycles, under fast 100 μs and low±16 V P/E pulses. These were achieved using Ge reaction with HfONtrapping layer to form the HfGeON, even at ultra-thin 2.5-nm ENT. Suchexcellent device integrity is unreachable for conventional Si₃N₄ CTFdevice due to nearly no trapping at 2-nm Si₃N₄.

Experiments

The MoN—[SiO₂—LaAlO₃]—[Ge—HfON]—[LaAlO₃—SiO₂]—Si MONOS CTF devices weremade on standard 6-in p-type Si wafers. The double tunnel oxide layersof 2.7-nm thick thermal SiO₂ was first grown on Si substrates andfollowed by depositing 2.5-nm thick LaAlO₃ by physical vapor deposition(PVD). Then the charge trapping layers of 8-nm thick HfON and 1.5-nmthick Ge were deposited by PVD. Next, a 6.5-nm thick LaAlO₃ wasdeposited by PVD and 6.5-nm thick SiO₂ was deposited by chemical vapordeposition (CVD) using Tetraethyl orthosilicate (Si(C₂H₅O)₄) to form thedouble blocking layers. Finally, a 200-nm thick MoN was deposited byPVD, followed by gate definition, reactive ion-etching (RIE),self-aligned 25 KeV P⁺ implantation at 5×10¹⁵ cm⁻² dose and 900° C. RTAto activate the dopant at source-drain region. The CTF devices were with10-μm gate length, 100-μm width and isolated by field oxide. Thefabricated devices were characterized by cross-sectional transmissionelectron microscopy (TEM), P/E, cycling and retention measurements to125° C.

FIGS. 14( a) and (b) show the schematic structure and energy banddiagram of the MoN—[SiO₂—LaAlO₃]—[Ge—HfON]—[LaAlO₃—SiO₂]—Si CTF device.An ultra-thin ENT of 2.5-nm was obtained from X-TEM. As shown in FIG.14( a), a flash memory 20 comprises a Si substrate 202, a SiO₂ layer 204formed on the Si substrate 202, a LaAlO₃ layer 206 formed on the SiO₂layer 204, a HfON layer 208 formed on the LaAlO₃ layer 206, a Ge/HfONlayer 210 (that is formed by reacting Ge with HfON) formed on the HfONlayer 208, another LaAlO₃ layer 212 formed on the Ge/HfON layer 210,another SiO₂ layer 214 formed on the another LaAlO₃ layer 212, and a MoNlayer 216 formed on the another SiO₂ layer 214. In an embodiment, theflash memory 20 may further comprise another HfON layer formed on theGe/HfON layer 210, and another Ge/HfON layer formed on the another HfONlayer. The energy band at top Ge/HfON may be narrowed due to the smallerbandgap of Ge (0.67 eV) and HfGeON formation. The small bandgap HfGeONlowers the E_(C) that improves the carrier retention. The band offset inLaAlO₃/SiO₂ double tunnel layers reduces the tunneling barrier forfaster P/E speeds and better endurance. The high-κ blocking and trappinglayers lower the P/E voltage, which in turn improves the erasesaturation due to the higher electric field across the thin tunnel SiO₂.

FIGS. 15( a) and (b) show the P/E characteristics of HfON and Ge/HfONCTF, respectively. The V_(th) increases with increasing P/E voltage andtime. The larger program V_(th) of Ge/HfON CTF indicates the bettertrapping capability than that of control HfON device. Small erasesaturation was obtained due to the using high-κ dielectrics to give alarger electric field in tunnel SiO₂ for better hole tunneling. Underthe ±16 V and 100 μs P/E, the V_(th) difference (ΔV_(th)) between P andE are 2.7 V and 4.4 V for HfON and Ge/HfON CTF devices, respectively.The larger ΔV_(th) memory window of Ge/HfON CTF than control HfON deviceis due to the Ge reaction with HfON to form the HfGeON that has higher-κfor better erase and higher traps for more efficient charge-trapping.

FIG. 16( a) shows the retention characteristics of HfON and Ge/HfON CTFdevices. Under the ±16 V and 100 μs P/E, the 10-year extrapolatedretention window at 125° C. for HfON CTF is 1.8 V that largely increasesto 3.2 V for Ge/HfON device. Such large 10-year retention window allowsmulti-level cell (MLC) storage at 125° C. with a record thinnest 2.5-nmENT. The good retention is due to the deep E_(C) of HfGeON for carrierstorage, like the deep-E_(C) of poly-Si FG flash memory. In addition,the larger physical thickness of high-κ-LaAlO₃/SiO₂ double barriersimproves the retention. Further, the large energy bandgap and small trapdensity of SiO₂, formed by CVD TEOS, in double barrier also helps theretention improvement. The fast 100 μs erase speed is due tobandgap-engineered lower hole barrier ΔE_(V) in the LaAlO₃/SiO₂ tunneloxide. The better trapping capability, faster P/E speed, and lower holetunnel barrier further lead to excellent endurance as shown in FIG. 16(b), with a larger 10⁶-cycled memory window of 3.6 V than the 2.2 V ofcontrol device, at the same ±16 V and 100 μs P/E. Such excellent cyclingdata are vitally important to allow further endurance improvement inhighly scaled CTF device with fewer stored electrons.

The record thinnest 2.5-nm ENT for CTF, large 10-year retention windowof 3.2 V at 125° C., and 10 ⁶ cycled endurance were reachedsimultaneously under fast 100 μs and low ±16V P/E, which fit therequirements of ITRS shown in Table 2.

Table 2 lists a variety of data published by ITRS in 2009.

TABLE 2 NAND Flash poly ½ Pitch (nm) 16 14 13 12 11 9 Cell size 04.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 area factor a inmultiples of F²SLC/MLC Tunnel SiO₂ or SiO₂ or SiO₂ or SiO₂ or SiO₂ orSiO₂ or dielectric ONO ONO ONO ONO ONO ONO material Tunnel 3-4 3-4 3-43-4 3-4 3-4 dielectric thickness EOT (nm) Blocking Al₂O₃ Al₂O₃ Al₂O₃Al₂O₃ Al₂O₃ Al₂O₃ dielectric material Blocking 6 5 5 5 5 5 dielectricthickness EOT (nm) Charge SiN/High-K SiN/High-K SiN/High-K SiN/High-KSiN/High-K SiN/High-K trapping layer material Charge 4-6 4-6 4-6 4-6 3-43-4 trapping layer thickness (nm) Gate material Metal Metal Metal MetalMetal Metal Highest W/E 15-17 15-17 15-17 15-17 15-17 15-17 voltage (V)Endurance 1.00E+04 1.00E+04 1.00E+04 1.00E+04 1.00E+04 1.00E+04(erase/write cycles) Nonvolatile  5-10  5-10  5-10  5-10  5-10  5-10data retention (years) Maximum 4 4 4 4 4 4 number of bits per cell (MLC)

The foregoing descriptions of the detailed embodiments are onlyillustrated to disclose the features and functions of the presentinvention and not restrictive of the scope of the present invention. Itshould be understood to those in the art that all modifications andvariations according to the spirit and principle in the disclosure ofthe present invention should fall within the scope of the appendedclaims.

1. A flash memory, comprising: a substrate; a first SiO₂ layer formed onthe substrate; a first high-κ layer formed on the first SiO₂ layer; ametal-implanted metal oxynitride layer formed on the first high-κ layer;a second high-κ layer formed on the metal-implanted metal oxynitridelayer; a second SiO₂ layer formed on the second high-κ layer; and a gatelayer formed on the second SiO₂ layer.
 2. The flash memory of claim 1,wherein the high-κ layer is made of a material of Al₂O₃, La₂O₃, HfO₂,ZrO₂, TiO₂, SiN or ternary or quarternary combinations thereof, themetal oxynitride layer is made of a material of AlON, LaON, HfON, ZrON,TiON, SiON or quarternary combinations thereof, and the metal-implantedmetal oxynitride layer includes As, Sb, Ga, or In.
 3. The flash memoryof claim 1, wherein the gate layer is made of metal or metal-nitride. 4.The flash memory of claim 3, wherein the metal-nitride is TiN, TaN orMoN 5-9. (canceled)
 10. A flash memory, comprising: a Si substrate; afirst SiO₂ layer formed on the Si substrate; a first high-κ layer formedon the first SiO₂ layer; a first oxynitride layer formed on the firsthigh-κ layer; a first metal/second metal oxynitride layer formed on thefirst oxynitride layer; a second high-κ layer formed on the firstmetal/second metal oxynitride layer; a second SiO₂ layer formed on thesecond high-κ layer; and a gate layer formed on the second SiO₂ layer.11. The flash memory of claim 10, further comprising: a secondoxynitride layer formed on the first metal/second metal oxynitridelayer; and a third metal/oxynitride layer formed on the secondoxynitride layer, wherein the second high-κ layer is directly formed onthe third metal/oxynitride layer.
 12. The flash memory of claim 10,wherein the high-κ layer is made of a material of Al₂O₃, La₂O₃, HfO₂,ZrO₂, TiO₂, SiN or ternary or quarternary combinations thereof, thesecond metal oxynitride layer is made of a material of AlON, LaON, HfON,ZrON, TiON, SiON or quarternary combinations thereof, the first metal isAs, Sb, Ga, or In, and the third metal is As, Sb, Ga, or In.
 13. Theflash memory of claim 10, wherein the gate layer is made of metal ormetal-nitride.
 14. The flash memory of claim 13, wherein themetal-nitride is TiN, TaN or MoN.